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SIMULATION
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WISPAC: a parallel array computer for large-scale system simulation

W.R. Cyre

Department of Electrical and Computer Engineering University of Wisconsin Madison, Wisconsin 53706

C.J. Davis

Department of Electrical and Computer Engineering University of Wisconsin Madison, Wisconsin 53706

A.A. Frank

Department of Electrical and Computer Engineering University of Wisconsin Madison, Wisconsin 53706

L. Jedynak

Department of Electrical and Computer Engineering University of Wisconsin Madison, Wisconsin 53706

M.J. Redmond

Department of Electrical and Computer Engineering University of Wisconsin Madison, Wisconsin 53706

V.C. Rideout

Department of Electrical and Computer Engineering University of Wisconsin Madison, Wisconsin 53706

This paper discusses the multiple-instruction stream/ multiple-data stream (MIMD) Wisconsin parallel array computer (WISPAC). The design of the computer makes use of current, low-cost microprocessor technology and is intended to meet future needs in large-scale simulation. A modular approach is taken where smaller configurations are meant as direct competi tive replacements of current hybrid systems. Larger configurations will allow high-speed solution of large-scale simulation problems using a one-to-one correspondence of each microprocessor to each node of the system being modeled. A three-dimensional configuration is used to allow a high degree of iso morphism between the computer setup and the model to be investigated. These schemes simplify programming requirements and overall machine conceptualization. New techniques of high-speed internode communication utilizing a serial "pass-through" scheme are des cribed. The scheme allows general cross-array com munication that is competitive with cross-point methods. Initial work on a minimal parallel config uration is also described.

SIMULATION, Vol. 29, No. 5, 165-172 (1977)
DOI: 10.1177/003754977702900525
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