Advanced Search

Journal Navigation

Journal Home

Subscriptions

Archive

Contact Us

Table of Contents

Sign In to gain access to subscriptions and/or personal tools.
SIMULATION
This Article
Right arrow Full Text (PDF)
Right arrow References
Right arrow Alert me when this article is cited
Right arrow Alert me if a correction is posted
Services
Right arrow Email this article to a friend
Right arrow Similar articles in this journal
Right arrow Alert me to new issues of the journal
Right arrow Add to Saved Citations
Right arrow Download to citation manager
Right arrowRequest Permissions
Right arrow Request Reprints
Right arrow Add to My Marked Citations
Citing Articles
Right arrow Citing Articles via Google Scholar
Right arrow Citing Articles via Scopus
Google Scholar
Right arrow Articles by Zimmerman, S. L.
Right arrow Articles by Robinson, J.P.
Right arrow Search for Related Content
Social Bookmarking
Add to CiteULike   Add to Complore   Add to Connotea   Add to Del.icio.us   Add to Digg   Add to Reddit   Add to Technorati   Add to Twitter  
What's this?

Other

Two-Level Cache Performance for Multiprocessors

Stanley L. Zimmerman

Rockwell International 400 Collins Rd., NE Cedar Rapids, IA 52498

J.P. Robinson

Electrical and Computer Engineering University of Iowa Iowa City, Iowa 52242

For shared bus multiprocessors operated in multiprogramming mode, the addition of second-level caches tends to significantly increase system performance. Trace-driven simulation was employed to obtain performance measurements over a range of system parameters, with the cache sizes at both levels being the parameters of most interest. For both light and heavy system loading, the addition of second-level caches was found to boost system performance. For heavily loaded multiprocessor cases, the workload-averaged percentage increases in performance ranged from 187% with 32k byte first-level caches to 507% with 4k byte first-level caches when 128k byte second- level caches were added. The main memory configuration and number of processors largely dictates the performance of a shared bus multiprocessor running in multiprogramming mode. The addition of larger second-level caches to the system results in increased system performance over a range of system configurations and workloads.

Key Words: two-level caches • shared bus multiprocessors • trace-driven simulation • RISC • SPARC • multilevel inclusion • cache coherence • multiprogramming • performance.

SIMULATION, Vol. 60, No. 4, 222-231 (1993)
DOI: 10.1177/003754979306000402
Add to CiteULike CiteULike   Add to Complore Complore   Add to Connotea Connotea   Add to Del.icio.us Del.icio.us   Add to Digg Digg   Add to Reddit Reddit   Add to Technorati Technorati   Add to Twitter Twitter    What's this?