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SIMULATION
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Simulation of Combinational Circuits for Fault Diagnosis

Sarma R. Vishnubhotla

Department of Computer Science and Engineering Oakland University Rochester, Michigan 48309

Simulation techniques are discussed to build test patterns to diagnose hardware faults in digital circuits. Only combinational circuits without redundant wires or undetectable faults are considered. All faults are assumed to be either stuck-at type faults or bridge-faults. An algorithm is presented to build test patterns, based on the circuit structure. The set of tests obtained from this algorithm is shown to have the diagnostic resolution to diagnose all the stuck-at type multiple faults and bridge-faults in the circuit. The simulation program accepts the circuit description as an input. It will store the details of the circuit in data structures that will enable the program to traverse both to the primary inputs and to the primary outputs from any wire. It is illustrated how the simulation program builds the test patterns, finds the fault ranges of each test and finally builds the fault dictionary of the circuit. A theory is presented to prove the completeness of the diagnostic resolution of the obtained test-set.

Key Words: Multiple stuck-at type faults • bridge-faults • simple paths • multiple paths • sub-paths • sensitizing criteria • sensitizing function • linked structures,simulation • fault ranges • fault dictionary.

SIMULATION, Vol. 60, No. 4, 235-245 (1993)
DOI: 10.1177/003754979306000404
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