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Trace Driven Pipeline and Cache Simulation of Multithreaded Computers

Dept. of Electrical and Computer Engineering McMaster University Hamilton, Ontario, Canada

Sumathi Srinivasan

Dept. of Electrical and Computer Engineering McMaster University Hamilton, Ontario, Canada

A technique for applying trace-driven simulation to cached multithreaded ma chines with dynamic thread scheduling is presented. A small amount of constraint information is added to each trace record, permitting the correct order of execution in the pipeline to be constructed. Strategies like context switching on a cache miss, in which the behaviour of the cache affects the instruction dispatch order, can be modelled with this technique.

The design of a multithreaded pipeline and cache trace-driven simulation system is described. This system allows thread- scheduled multithreaded processors, which are not simulatable by conventional trace- driven techniques, to be efficiently and accurately simulated. Sample simulation results illustrate the flexibility of this simulation technique.

Key Words: Multithreaded computers • trace-driven simulation • thread scheduling.

SIMULATION, Vol. 63, No. 2, 75-82 (1994)
DOI: 10.1177/003754979406300201


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